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vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 1 02/12/01 ? vitesse semiconductor corporation ? 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com features general description the VSC838 is a monolithic 36x36 asynchronous crosspoint switch, designed to carry broadband data streams. the VSC838 also has an internal 37 th output channel which is used in conjunction with the activity monitor to allow in system diagnostics. a high degree of signal integrity is maintained throughout the chip via fully differential signal paths. the crosspoint function is based on a multiplexer array architecture. each data output is driven by a 36:1 multiplexer that can be programmed to one and only one of its 36 inputs. the signal path is unregistered and fully asynchronous, so there are not any restrictions on the phase, frequency, or signal pattern at each input. each high-speed output is a fully differential, switched current driver with switchable on-die terminations for maximum signal integrity. data inputs are terminated on-die through 100 ? impedance between true and complement inputs (see input termination section for further details). a dual mode programming interface is provided that allows programming commands to be sent as serial data or parallel data. core programming can be random for each port address, or multiple program assignments can be queued and issued simultaneously. the programming may be initialized to a ?straight-through? configu- ration (a0 to y0, a1 to y1, etc.) using the init pin. unused channels may be powered down to allow efficient use of the switch in applications that require only a subset of the channels. power-down can be accomplished in hardware, via dedicated power pins for pairs of input and output channels, or in software by programming individual unused outputs with a disable code. VSC838 block diagram 36 input by 37 output crosspoint switch 3.2gb/s nrz data bandwidth non-blocking architecture broadcast and multicast capabilities lvttl/2.5v cmos control i/o (3.3v tolerant) input signal activity monitoring function integrated signal equalization (ise) for deterministic jitter reduction 66mhz dual programming port parallel and serial programming modes programmable on-chip i/o termination differential cml output drivers single 2.5v supply 6w typical ? low drive mode 7w typical ? high drive mode high performance 37.5mm, 480 tbga package 2 2 2 2 a0 a35 y0 y35 p control
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 2 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com functional block diagram 36 x 37 switch core core program registers a, an[0:35] y, yn[0:35] program memory program interface outchan [5:0] inchan [5:0] activity monitor init config sdout serial cs load ale_scn actclk activity 37 th output actchan internal
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 3 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com functional description input / output characteristics all input data must be differential and should be nominally biased to +2.0v or ac-coupled. other levels are allowed as described under the input termination section. on-chip terminations are provided, with a nomi- nal impedance of 100 ? differential. all input termination resistors float with an internal bias provided for ac- coupling. for direct interconnection of multiple VSC838 devices, a cml termination mode is provided by tying the itc pin to v cc , which ties the center point of the 100 ? termination to v cc , causing the terminations to act as loads for an open-drain or open-collector differential output. data outputs are provided through differential current switches with on-chip back-termination. the output circuit is capable of driving external 50 ? far-end termination (recommended). the output back-terminations are electronically switchable to enable a power savings of 1w (max) by reducing the output driver current. programming interface parallel mode in parallel mode (serial=0), the binary word on inchan[5:0] is the numerical identifier of the input that will be routed to the specified output. outchan[5:0] is the numerical identifier of the output being pro- grammed. a rising edge on the load signal will transfer the programming data to the shadow register in the program memory. raising config (asynchronously) will transfer the programming data to the main latches in the program memory and cause the internal select signals in the core to re-configure the multiplexer. lowering config will latch the main latches. config may be tied high to enable programming to take effect instan- taneously. this interface may be used with multiplexed address/data buses by using only inchan[5:0] without outchan[5:0] and dropping ale when the address of the output to be programmed is present on inchan[5:0]. after the address is latched, the input address may be presented on inchan[5:0] and pro- gramming proceeds as above. no read-back capability is provided in parallel mode. read-back for diagnostic purposes is provided in serial mode via the scan function. serial mode in serial mode (serial=1), the inchan[0] pin becomes the serial data input sdin and the inchan[1] pin becomes the serial clock sclk (rising edge triggered). a serial word of the form [output][input] is shifted into the internal shift register, and the load pin is asserted (high) coincident with the last bit of the data word to signal that the word is to be applied. this transfers the input identifier to the shadow register of the addressed output. config is then applied (asynchronously) to transfer one or more program commands to the main latches of the program memories. the sdout pin follows the data on the inchan[0](sdin) pin 14 clock cycles later. this enables the user to chain the serial ports of several crosspoints, shift program data for all switches through such a chain, and assert load on all switches simultaneously to program all of the connections simultaneously. the output field is 7 bits long, representing the binary numerical identifier of the output to be programmed. the input field is 7 bits long, representing the numerical identifier of the input that will be routed to the speci- fied output.
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 4 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com serial read-back read-back of the program memory contents is accomplished in serial mode by setting the ale_scn pin high. this will serially shift out the contents of the main latches in the program memories, slice 36 first and slice 0 last, and msb-first, lsb-last for each 7-bit word (see figure 3). one rising edge of inchan[1](sclk) with ale_scn=0 and serial=1 must occur to load the entire 483-bit shift register prior to shifting out data. at a clock rate of 66mhz, this operation takes 7.26 s. activity monitoring the activity monitor observes the output of the internal 37 th output from the core. by programming the 37 th output to observe various inputs, the input signals can be scanned for activity or lack thereof. each rising edge of actclk causes the monitor to read out the activity state from the previous actclk period and clears the internal activity state until a data transition triggers it again. there must be a minimum of one rising and one falling edge on the observed input data pin during the actclk period for activity to be detected. after power- on the output of activity after the first actclk rising edge is unknown. to access the 37 th output, actchan and inchan[5] must both be high. selective power-down unused input and output channels can be made to consume little or no power via one of two methods of selective power-down. software power-down using this feature, unused outputs may be disabled, saving approximately 170 mw per channel for maxi- mum dissipation conditions. this is accomplished by programming each unused output to look at input 127 (7f hex), which represents a non-existent input channel. the channel may be subsequently activated by program- ming a valid input address. it is recommended, however, that any changes in power programming only be exe- cuted as part of an initialization sequence to guard against the effects of any switching transients that might result from changing the power supply current suddenly. software mode does not affect the functioning or power of unused input channels. hardware power-down using this feature, the power associated with given pairs of inputs may be shut off by tying the correspond- ing v ee pin to v cc (see table 10). approximately 160 mw per input pair is saved under the maximum dissipa- tion conditions. the power associated with given pairs of outputs, including their contribution to the core power, can be shut off by tying the corresponding v ee pin to v cc (see table 10). approximately 360 mw per output pair is saved under the maximum dissipation conditions. certain v ee pins must always be active. in other words, tied to the most negative supply, so the correspond- ing inputs and outputs will always be on and consuming power. see figure 7 and table 10 for the location of these pins.
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 5 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com ac characteristics table 1: data path notes: (1) tested on a sample basis only. (2) broadband (unfiltered) deterministic jitter added to a jitter-free input, 2 23 -1 prbs data pattern. table 2: program interface timing parameter description min typ max units f rate maximum data rate - - 3.2 gb/s t skw channel-to-channel delay skew - 300 - ps t pday propagation delay from an a input to a y output - 750 - ps t r , t f high-speed input rise/fall times, 20% to 80% - - 150 ps t r , t f high-speed output rise/fall times, 20% to 80% - - 150 ps t jr output added delay jitter, rms (1, 2) -10ps t jp output added delay jitter, peak-to-peak (1, 2) -40ps parameter description min typ max units t swr setup time from inchan[5:0] or outchan5:0] to rising edge of wr . 3.35 ?? ns t hwr hold time from rising edge of wrb to inchan[5:0] or outchan[5:0]. 1.45 ?? ns t pwlw pulse width (high or low) on load 6.75 ?? ns t scs setup time from cs to falling edge of load or ale_scn in parallel or burst mode, or rising edge of load in serial mode. 0 ?? ns t hcsb hold time of cs rising edge after load or ale_scn rising in parallel or burst mode, or falling edge of load in serial mode, or falling edge of config in any mode. 0 ?? ns t pwcfg pulse width (high or low) on config. 6.75 ?? ns t ssdin setup time from inchan0(sdin) to inchan1(sclk) rising. 1.65 ?? ns t hsdin hold time of inchan0(sdin) after inchan1(sclk) rising. 1.0 ?? ns t persclk minimum period of sclk in serial mode. 15 ?? ns t sload setup time from load to inchan1(sclk) rising. 1.85 ?? ns t hload hold time of load after inchan1(sclk) rising. 0.95 ?? ns t sserial setup time from serial rising to inchan1(sclk) rising when entering serial mode or serial falling to load falling when entering parallel mode or serial falling to load rising when entering burst mode. 0.90 ?? ns t hserial hold time from inchan1(sclk) rising to serial falling when exiting serial mode. 0 ?? ns t dsdout delay from inchan1(sclk) rising to sdout, 20pf load. ?? 6.20 ns t pwinit pulse width (high or low) on init .6.75 ?? ns t sscan setup time from ale_scn to inchan1(sclk) rising when starting or completing a serial read-back sequence. 1.65 ?? ns t hscan hold time of ale_scn after inchan1(sclk) rising when starting or completing a serial read-back sequence. 1.0 ?? ns
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 6 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 1: parallel mode -- separate address/data (leave ale_scn pin high) figure 2: parallel mode -- multiplexed address/data outchan[5:0] inchan[5:0] load config output addr input addr t pwlw t pwcfg serial t sserial cs t scs t swr t hwr t hcs inchan[5:0] load config output addr input addr t pwlw t pwcfg ale_scn serial t sserial t scs cs t hwr t swr t hcs
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 7 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 3: serial mode (leave ale_scn pin low during programming) figure 4: serial read-back note: the word pattern during serial read back will be four valid words followed by four ? don ? t care ? words. sdout load config t hsdin t pwcfg inchan1_sclk inchan0_sdin y5 y4 y3 y2 low y1 y0 a5 a4 a3 a2 low a1 a0 y5 y4 y3 y2 t ssdin serial t sserial t dsdout t hload t sload t persclk cs t scs t hcs y(n) = output address bit (n); a(n) = input address bit (n) sdout ale_scn t sscan inchan1_sclk 36 b5 t hscan serial t sserial t dsdout 36 b4 36 b3 36 b2 36 b1 36 b0 35 b5 35 b4 35 b3 35 b2 35 b1 35 b0 34 b5 msb of program memory for activity monitor channel read-back shift register (483 bits long) is loaded here on rising edge of inchan1_sclk with serial high and ale_scn low t persclk 36 low 35 low msb of program memory for 36 th output channel
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 8 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com dc characteristics all characteristics are over the specified operating conditions. table 3: power supply requirements table 4: control port input levels (lvttl/cmos) table 5: signal input levels (high-speed signal path) table 6: signal output levels (high-speed signal path) , term_ctrl=on, drive_ctrl=hi notes: (1) mean peak-to-peak amplitude measurement of either true or complement of the differential signal. (2) v cc = v ccp = 2.5v, v ee = 0v. (3) terminated in 50 ? to v cc . this termination is used for testing the part, but other terminations are allowed?see table 9. parameter description min typ max units conditions i cc v cc supply current 2,286 3,428 ma p t total chip power (with i term = 0 and back-terminations on, high drive) 69w max p t is with +5% supply, +85 c case temperature and high drive parameter description min typ max units conditions v ih input high voltage 1.7 v cc +1.0 v v il input low voltage 0 0.8 v i ih input high current tbd ma i il input low current tbd ma v oh output high voltage v cc -0.2 v cc v dc load < 500a v ol output low voltage 0 0.2 v dc load < 2ma v ohpu v oh with external pull-up 2.4 v 250 ? to 3.3v(5%) v olpu v ol with external pull-up 0.4 v 250 ? to 3.3v(5%) parameter description min typ max units conditions v in input voltage amplitude 150 1100 mv see note 1 v icm input common-mode voltage v cc -0.7 v cc -0.2 v see note 2 parameter description min typ max units conditions v out output differential voltage 400 600 mv see note 1, 3 v ocm output common-mode voltage v cc -0.3 v cc -0.2 v see note 2, 3
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 9 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com i/o equivalent circuits input termination the high-speed inputs of the VSC838 are internally terminated by a 100 ? impedance between true and complement inputs. termination resistors are isolated from each other on-chip. the termination will self-bias to +2.0v (nominal) for ac-coupled applications. the itc pin enables direct interconnection of multiple VSC838 devices. with itc tied to v cc , the center point of the 100 ? termination impedance is tied to v cc , causing the terminations to act as loads for an open-drain or open-collector differential output. table 7: allowed input termination schemes some allowed termination schemes result in additional i cc current and power dissipation on-chip. see table 8. table 8: additional current and power type description comments 1 ac-coupled input tie itc low, 100 ? differential input termination, input self-biased 2 dc-coupled from open-drain cml tie itc high, terminations acts as 50 ? load to v cc 3 dc-coupled from back-terminated 2.5v cml tie itc high, terminations acts as 50 ? load to v cc 4 dc-coupled from back-terminated 2.5v cml tie itc low, 100 ? differential termination (preferred over type 3) 5 dc-coupled from back-terminated 3.3v lv-pecl tie itc low, 100 ? differential termination parameter description min typ max units conditions i cc-c additional icc current when receiving dc- coupled cml (itc = high) 180 ma p cc-c additional power dissipated on-chip for dc terminating cml at inputs 0.180 w pad pad 50 50 h/s input equivalent circuit h/s output equivalent circuit pad pad 50 50 vcc itc term_ctrl drive_ctrl
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 10 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com output termination the high-speed outputs of the VSC838 are internally back terminated by 50 ? to v cc when the term_ctrl pin is high. when this pin is low, the output driver functions as an open-drain cml driver. setting drive_ctrl low (gnd) saves 1w under maximum power dissipation conditions. see table 9 for allowable types of terminations and modes of operation. table 9: allowed high-speed output terminations and modes of operation note: (1) measured at output of VSC838, with v cc = 2.5v. absolute maximum ratings (1) power supply voltage (v cc ) potential to gnd ..............................................................................-0.5v to +4.0v lvttl input voltage applied ................................................................................................-0. 5v to v cc +1.0v ecl input voltage applied ....................................................................................................- 0.5v to v cc +0.5v output current (i out ) .............................................................................................................................. ...... 50ma case temperature under bias (t c ) ............................................................................................. -55 o c to + 125 o c storage temperature (t stg ) ........................................................................................................ -65 o c to + 150 o c note: (1) caution: stresses listed under ? absolute maximum ratings ? may be applied to devices one at a time without causing perma- nent damage. functionality at or exceeding the values listed is not implied. exposure to these values for extended periods may affect device reliability. operating conditions supply voltage (v ee ).............................................................................................................................. ............ 0v supply voltage (v cc ) ............................................................................................................................+2 .5v 5% supply voltage (v ccp )...........................................................................................................................+2. 5v 5% case temperature operating range (t)..................................................... 0 o c to 85 o cpackage pin descriptions type description drive_ ctrl term_ ctrl v od (1) (mv) typ v ocm (1) (v) typ 1 ac-coupled to 50 ? termination to any voltage v cc (high) v cc (on) 500 2.0 2 ac-coupled to 100 ? differential termination v cc (high) v cc (on) 500 2.0 3 dc-coupled, terminated in 50 ? to v cc at far-end only gnd (low) gnd (off) 500 2.25 4 dc-coupled, terminated in 50 ? to v cc at far-end only v cc (high) gnd (off) 1000 2.0 5 dc-coupled, source and far-end terminated in 50 ? to v cc gnd (low) v cc (on) 250 2.375 6 dc-coupled, source and far-end terminated in 50 ? to v cc v cc (high) v cc (on) 500 2.25 7 dc-coupled, 100 ? differential termination gnd (low) v cc (on) 250 2.25 8 dc-coupled, 100 ? differential termination v cc (high) v cc (on) 500 2.0
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 11 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com figure 5: pinout diagram -- bottom view 0 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 654321 48 10 12 14 16 18 20 24 22 26 28 30 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag 3 159 711 13 17 15 19 23 21 25 27 29 31 1 5 9 13 17 3 7 11 15 19 23 21 25 29 27 31 0 2 610 48 14 12 16 18 20 22 24 26 30 28 32 inputs [an, ann] outputs [yn, ynn] inputs [an, ann] outputs [yn, ynn] ball grid index 2 32 34 35 34 33 6 28 29 ah aj 33 35 outchan4 outchan5 outchan0 outchan1 outchan3 outchan2 actchan sdout serial activity actclk cmv drive_ctrl term_ctrl inchan3 inchan2 inchan1(sclk) inchan0(sdin) inchan5 ale_scn inchan4 itc load init cs config nc nc nc nc nc nc nc nc nc nc nc nc vcc dedicated vee common vee (always on) control port 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 654321 28 29 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 12 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com table 10: package pin indentifications signal name ball description level high-speed data inputs a0, an0 d23, e23 high-speed data input channel 0; true, complement pecl a1, an1 ah23, aj23 high-speed data input channel 1; true, complement pecl a2, an2 b23, a23 high-speed data input channel 2; true, complement pecl a3, an3 af23, ae23 high-speed data input channel 3; true, complement pecl a4, an4 d21, e21 high-speed data input channel 4; true, complement pecl a5, an5 ah21, aj21 high-speed data input channel 5; true, complement pecl a6, an6 b21, a21 high-speed data input channel 6; true, complement pecl a7, an7 af21, ae21 high-speed data input channel 7; true, complement pecl a8, an8 d19, e19 high-speed data input channel 8; true, complement pecl a9, an9 ah19, aj19 high-speed data input channel 9; true, complement pecl a10, an10 b19, a19 high-speed data input channel 10; true, complement pecl a11, an11 af19, ae19 high-speed data input channel 11; true, complement pecl a12, an12 d17, e17 high-speed data input channel 12; true, complement pecl a13, an13 ah17, aj17 high-speed data input channel 13; true, complement pecl a14, an14 b17, a17 high-speed data input channel 14; true, complement pecl a15, an15 af17, ae17 high-speed data input channel 15; true, complement pecl a16, an16 d15, e15 high-speed data input channel 16; true, complement pecl a17, an17 ah15, aj15 high-speed data input channel 17; true, complement pecl a18, an18 b15, a15 high-speed data input channel 18; true, complement pecl a19, an19 af15, ae15 high-speed data input channel 19; true, complement pecl a20, an20 d13, e13 high-speed data input channel 20; true, complement pecl a21, an21 ah13, aj13 high-speed data input channel 21; true, complement pecl a22, an22 b13, a13 high-speed data input channel 22; true, complement pecl a23, an23 af13, ae13 high-speed data input channel 23; true, complement pecl a24, an24 d11, e11 high-speed data input channel 24; true, complement pecl a25, an25 ah11, aj11 high-speed data input channel 25; true, complement pecl a26, an26 b11, a11 high-speed data input channel 26; true, complement pecl a27, an27 af11, ae11 high-speed data input channel 27; true, complement pecl a28, an28 d9, e9 high-speed data input channel 28; true, complement pecl a29, an29 ah9, aj9 high-speed data input channel 29; true, complement pecl a30, an30 b9, a9 high-speed data input channel 30; true, complement pecl a31, an31 af9, ae9 high-speed data input channel 31; true, complement pecl a32, an32 d7, e7 high-speed data input channel 32; true, complement pecl a33, an33 ah7, aj7 high-speed data input channel 33; true, complement pecl a34, an34 b7, a7 high-speed data input channel 34; true, complement pecl a35, an35 af7, ae7 high-speed data input channel 35; true, complement pecl
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 13 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com high-speed data outputs y0, yn0 g28, g29 high-speed data output channel 0; true, complement cml y1, yn1 g4, g5 high-speed data output channel 1; true, complement cml y2, yn2 g26, g25 high-speed data output channel 2; true, complement cml y3, yn3 g2, g1 high-speed data output channel 3; true, complement cml y4, yn4 j28, j29 high-speed data output channel 4; true, complement cml y5, yn5 j4, j5 high-speed data output channel 5; true, complement cml y6, yn6 j26, j25 high-speed data output channel 6; true, complement cml y7, yn7 j2, j1 high-speed data output channel 7; true, complement cml y8, yn8 l28, l29 high-speed data output channel 8; true, complement cml y9, yn9 l4, l5 high-speed data output channel 9; true, complement cml y10, yn10 l26, l25 high-speed data output channel 10; true, complement cml y11, yn11 l2, l1 high-speed data output channel 11; true, complement cml y12, yn12 n28, n29 high-speed data output channel 12; true, complement cml y13, yn13 n4, n5 high-speed data output channel 13; true, complement cml y14, yn14 n26, n25 high-speed data output channel 14; true, complement cml y15, yn15 n2, n1 high-speed data output channel 15; true, complement cml y16, yn16 r28, r29 high-speed data output channel 16; true, complement cml y17, yn17 r4, r5 high-speed data output channel 17; true, complement cml y18, yn18 r26, r25 high-speed data output channel 18; true, complement cml y19, yn19 r2, r1 high-speed data output channel 19; true, complement cml y20, yn20 u28, u29 high-speed data output channel 20; true, complement cml y21, yn21 u4, u5 high-speed data output channel 21; true, complement cml y22, yn22 u26, u25 high-speed data output channel 22; true, complement cml y23, yn23 u2, u1 high-speed data output channel 23; true, complement cml y24, yn24 w28, w29 high-speed data output channel 24; true, complement cml y25, yn25 w4, w5 high-speed data output channel 25; true, complement cml y26, yn26 w26, w25 high-speed data output channel 26; true, complement cml y27, yn27 w2, w1 high-speed data output channel 27; true, complement cml y28, yn28 aa28, aa29 high-speed data output channel 28; true, complement cml y29, yn29 aa4 , aa5 high-speed data output channel 29; true, complement cml y30, yn30 aa26, aa25 high-speed data output channel 30; true, complement cml y31, yn31 aa2, aa1 high-speed data output channel 31; true, complement cml y32, yn32 ac28, ac29 high-speed data output channel 32; true, complement cml y33, yn33 ac4, ac5 high-speed data output channel 33; true, complement cml y34, yn34 ac26, ac25 high-speed data output channel 34; true, complement cml y35, yn35 ac2, ac1 high-speed data output channel 35; true, complement cml signal name ball description level
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 14 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com control pins actclk ad2 clock for activity monitor (<10mhz) lvttl activity ad1 activityresult from previous actclk period lvttl ale_scn ad25 address latch enable for multiplexed parallel mode; scan enable for serial mode. see figures 2 through 6 for proper use. lvttl cmv ad3 output drive current control (leave floating) analo g config f27 logic high transfers programming to main program memory lvttl cs af6 chip select (active low) lvttl drive_ctrl ad4 output drive current switch (low = 10ma, high = 20ma) lvttl inchan0 (sdin) ag24 input channel, bit 0 and serial data in serial mode lvttl inchan1 (sclk) af24 input channel, bit 1 and serial clock in serial mode lvttl inchan2 ah24 input channel, bit 2 lvttl inchan3 aj24 input channel, bit 3 lvttl inchan4 ad27 input channel, bit 4 lvttl inchan5 ad26 input channel, bit 5 lvttl init aj6 init = 0 forces ? straight-through ? program lvttl itc ad29 input termination control (gnd = floating input termination, v cc = cml mode. see table 7). analo g load ad28 rising edge writes data in parallel and burst modes, see figure 5 for serial mode lvttl outchan0 f1 output channel, bit 0 lvttl outchan1 f2 output channel, bit 1 lvttl actchan f5 activity channel enable bit; high = enable lvttl outchan2 f4 output channel, bit 2 lvttl outchan3 f3 output channel, bit 3 lvttl outchan4 a6 output channel, bit 4 lvttl outchan5 b6 output channel, bit 5 lvttl sdout ag6 serial data out for serial mode and scan lvttl serial ae6 serial = 1 (sets serial mode) lvttl term_ctrl ad5 output back-termination control (low = no back term; high = 50 ? back-termination to v cc . see table 9). lvttl signal name ball description level
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 15 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com power supplies nc d22, ah22, b22, af22 d20, ah20, b20, af20 d18, ah18, b18, af18 d16, ah16, b16, af16 d14, ah14, b14, af14 d12, ah12, b12, af12 d10, ah10, b10, af10 d8, ah8, b8, af8 e22, aj22, a22, ae22 e20, aj20, a20, ae20 e18, aj18, a18, ae18 e16, aj16, a16, ae16 e14, aj14, a14, ae14 e12, aj12, a12, ae12 e10, aj10, a10, ae10 e8, aj8, a8, ae8 no connect nc h28, h4, h26, h2 k28, k4, k26, k2 m28, m4, m26, m2 p28, p4, p26, p2 t28, t4, t26, t2 v28, v4, v26, v2 y28, y4, y26, y2 ab28, ab4, ab26, ab2 h29, h5, h25, h1 k29, k5, k25, k1 m29, m5, m25, m1 p29, p5, p25, p1 t29, t5, t25, t1 v29, v5, v25, v1 y29, y5, y25, y1 ab29, ab5, ab25, ab1 no connect nc e6, d6, c6 a24, b24, d24, e24, c24 f29, f28, f25, f26 no connect vee c23, c7, r3, ag7 ag23, r27, ah6, ae24p common negative power supply gnd signal name ball description level
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 16 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com vcc a1, a2, a3, a4, a5 b1, b2, b3, b4, b5 c1, c2, c3, c4, c5 d1, d2, d3, d4, d5 e1, e2, e3, e4, e5 a25, a26, a27, a28, a29 b25, b26, b27, b28, b29 c25, c26, c27, c28, c29 d25, d26, d27, d28, d29 e25, e26, e27, e28, e29 ae1, ae2, ae3, ae4, ae5 af1, af2, af3, af4, af5 ag1, ag2, ag3, ag4, ag5 ah1, ah2, ah3, ah4, ah5 aj1, aj2, aj3, aj4, aj5 ae25,ae26,ae27,ae28,a e29 af25,af26,af27,af28,a f29 ag25,ag26,ag27,ag28, ag29 ah25,ah26,ah27,ah28, ah29 aj25,aj26,aj27,aj28,aj2 9 positive power supply 2.5v nc c22, c20, c18, c16, c14, c12, c10, c8, ag22, ag20, ag18, ag16, ag14, ag12, ag10, ag8, h3, k3, m3, p3, t3, v3, y3, ab3, h27, k27, m27, p27, t27, v27, y27, ab27, no connect veep_t1 c21 negative power supply for inputs a4/an4 + a6/an6 gnd veep_t2 c19 negative power supply for inputs a8/an8 + a10/an10 gnd veep_t3 c17 negative power supply for inputs a12/an12 + a14/an14 gnd veep_t4 c15 negative power supply for inputs a16/an16+a18/an18 gnd veep_t5 c13 negative power supply for inputs a20/an20+a22/an22 gnd veep_t6 c11 negative power supply for inputs a24/an24+a26/an26 gnd veep_t7 c9 negative power supply for inputs a28/an28+a30/an30 gnd veep_b1 ag21 negative power supply for inputs a5/an5+a7/an7 gnd veep_b2 ag19 negative power supply for inputs a9/an9+a11/an11 gnd veep_b3 ag17 negative power supply for inputs a13/an13+a15/an15 gnd veep_b4 ag15 negative power supply for inputs a17/an17+a19/an19 gnd veep_b5 ag13 negative power supply for inputs a21/an21+a23/an23 gnd signal name ball description level
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 17 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com veep_b6 ag11 negative power supply for inputs a25/an25+a27/an27 gnd veep_b7 ag9 negative power supply for inputs a29/an29+a31/an31 gnd veep_l0 g3 negative power supply for outputs y1/yn1+y3/yn3 gnd veep_l1 j3 negative power supply for outputs y5/yn5+y7/yn7 gnd veep_l2 l3 negative power supply for outputs y9/yn9+y11/yn11 gnd veep_l3 n3 negative power supply for outputs y13/yn13+y15/yn15 gnd veep_l4 u3 negative power supply for outputs y21/yn21+y23/yn23 gnd veep_l5 w3 negative power supply for outputs y25/yn25+y27/yn27 gnd veep_l6 aa3 negative power supply for outputs y29/yn29+y31/yn31 gnd veep_l7 ac3 negative power supply for outputs y33/yn33+y35/yn35 gnd veep_r0 g27 negative power supply for outputs y0/yn0+y2/yn2 gnd veep_r1 j27 negative power supply for outputs y4/yn4+y6/yn6 gnd veep_r2 l27 negative power supply for outputs y8/yn8+y10/yn10 gnd veep_r3 n27 negative power supply for outputs y12/yn12+y14/yn14 gnd veep_r4 u27 negative power supply for outputs y20/yn20+y22/yn22 gnd veep_r5 w27 negative power supply for outputs y24/yn24+y26/yn26 gnd veep_r6 aa27 negative power supply for outputs y28/yn28+y30/yn30 gnd veep_r7 ac27 negative power supply for outputs y32/yn32+y34/yn34 gnd signal name ball description level
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 18 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com package information - 37.5mm 480 bga 00.30 s c a s b s
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch g52351-0, rev 3.0 page 19 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com ordering information the order number for this product is formed by a combination of the device type and package type. notice vitesse semiconductor corporation ( ? vitesse ? ) provides this document for informational purposes only. this document contains pre-production information about vitesse products in their concept, development and/or testing phase. all information in this document, includ ing descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. n othing contained in this document shall be construed as extending any warranty or promise, express or implied, that any vitesse product will be availabl e as described or will be suitable for or will accomplish any particular task. vitesse products are not intended for use in life support appliances, devices or systems. use of a vitesse product in such appl ications without writ- ten consent is prohibited. VSC838 xx device type package style ug: 480 tbga, 37.5mm body oc-48 36x37 crosspoint switch
vitesse semiconductor corporation preliminary data sheet VSC838 3.2gb/s 36x37 crosspoint switch page 20 g52351-0, rev 3.0 02/12/01 ? vitesse semiconductor corporation 741 calle plano camarillo, ca 93012 tel: (800) vitesse fax: (805) 987-5896 email: prodinfo@vitesse.com internet: www.vitesse.com

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